1. Technical Field
The present invention relates to a circuit and method of generating a voltage of a semiconductor memory apparatus, and more particularly, to a circuit and method of generating a voltage of a semiconductor memory apparatus to maintain stable a potential level of an internal voltage.
2. Related Art
In general, dynamic random access memories (DRAMs) use a core voltage VCORE when high-level data is written in a memory cell. Specifically, the DRAM includes a core voltage generating circuit that generates a core voltage VCORE according to an external voltage VDD. The core voltage VCORE is applied to a bit line (herein, a bit line serves as a drain of a cell transistor), and may be stored as high-level data in a capacitor that is connected to the cell transistor. However, as the external voltage VDD increase, the core voltage VCORE goes upper. Excessive operating of the core voltage generating circuit increases and outputs the core voltage VCORE. A bit line precharge voltage VBLP that is generated from the core voltage VCORE is also increased.
Meanwhile, in normal mode, a boot strapped voltage VPP that is applied to a gate of a cell transistor and a threshold voltage Vth of the cell transistor are constant. Accordingly, though the core voltage VCORE is increased, a whole voltage level of the raised core voltage VCORE is not securely stored, the core voltage VCORE is stored as a high-level data in a capacitor connected to the cell transistor. However, the bit line precharge voltage VBLP is increased due to the increased core voltage VCORE. Accordingly, when a sense amplifier is operated, a small voltage ΔV charge shared voltage between a voltage level of the high-level data that is stored in a capacitor and bit line causes a defect in a DRAM. For this reason, the core voltage VCORE can maintain itself stable, whether the external voltage VDD is low or not. Therefore, the semiconductor memory apparatus uses a core voltage maintaining circuit that decreases the core voltage VCORE when the core voltage VCORE increases. Such that the core voltage VCORE is reduced from being changed according to the external voltage VDD to stably supply the core voltage VCORE. As a result, an internal circuit that received the core voltage VCORE can perform a stable operation.
Meanwhile, a burn-in test mode is a test process that applies a stress test to the DRAM to detect defective cells in advance. That is, during the burn-in test mode, the stress test is applied to the DRAM over a long period of time to detect the defective cells. For example, a high temperature and a high voltage are applied to the DRAM to detect the defective cells.
During the burn-in test mode, a voltage that is higher than the bootstrapped voltage VPP is applied to a gate of a cell transistor. However, when the increased core voltage VCORE is applied to a bit line, the core voltage VCORE is equal to or higher than a predetermined threshold voltage. Thus, the core voltage VCORE as high-level data may be stored in a capacitor of a cell transistor. Further, even when the bit line precharge voltage VBLP is increased due to the increased core voltage VCORE the increased core voltage VCORE is already stored in the capacitor that is connected to the cell transistor, and the small voltage ΔV that is to be charge-shared is not decreased. The small voltage ΔV during the burn-in test mode may be larger than the small voltage ΔV during the normal mode. Accordingly, during the burn-in test mode, the operation of the core voltage maintaining circuit becomes a supplemental operation, which causes unnecessary power consumption.